1. Field of the Invention
The present disclosure generally relates to the field of fabricating integrated circuits, and, more particularly, to a semiconductor device with DRAM bit lines made from the same material as the gate electrodes in non-memory regions of the device, and methods of making the same.
2. Description of the Related Art
In modern integrated circuits, a very high number of individual circuit elements, such as field effect transistors in the form of CMOS, NMOS, PMOS elements, resistors, capacitors and the like, are formed on a single chip area. Typically, feature sizes of these circuit elements are steadily decreasing with the introduction of every new circuit generation, to provide currently available integrated circuits with high performance in terms of speed and/or power consumption. A reduction in size of transistors is an important aspect in steadily improving device performance of complex integrated circuits, such as CPUs. The reduction in size commonly brings about an increased switching speed, thereby enhancing signal processing performance, while, however, increasing dynamic power consumption of the individual transistors. That is, due to the reduced switching time interval, the transient currents upon switching a MOS transistor element from logic low to logic high are significantly increased.
In addition to the large number of transistor elements, a plurality of passive circuit elements, such as capacitors, are typically formed in integrated circuits that are used for a plurality of purposes, such as charge storage for storing information, for decoupling and the like. Decoupling in integrated circuits is an important aspect for reducing the switching noise of the fast switching transistors, since the decoupling capacitor may provide energy at a specific point of the circuitry, for instance at the vicinity of a fast switching transistor, and thus reduce voltage variations caused by the high transient currents which may otherwise unduly affect the logic state represented by the transistor.
Due to the decreased dimensions of circuit elements, not only the performance of the individual transistor elements may be increased, but also their packing density may be improved, thereby providing the potential for incorporating increased functionality into a given chip area. For this reason, highly complex circuits have been developed, which may include different types of circuits, such as analog circuits, digital circuits and the like, thereby providing entire systems on a single chip (SoC). Furthermore, in sophisticated micro-controller devices and other sophisticated devices, an increasing amount of storage capacity may be provided on chip with the CPU core, thereby also significantly enhancing the overall performance of modern computer devices. For example, in typical micro-controller designs, different types of storage devices may be incorporated so as to provide an acceptable compromise between die area consumption and information storage density versus operating speed. For example, static RAM memories may be formed on the basis of registers, thereby enabling an access time determined by the switching speed of the corresponding transistors in the registers. Typically, a plurality of transistors may be required to implement a corresponding static RAM cell, thereby significantly reducing the information storage density compared to, for instance, dynamic RAM (DRAM) memories including a storage capacitor in combination with a pass transistor. Thus, a higher information storage density may be achieved with DRAMs, although at a reduced access time compared to static RAMs, which may nevertheless render dynamic RAMs attractive in complex semiconductor devices.
Complex integrated circuit devices typically include a memory array, such as an embedded DRAM array, and other non-memory circuits, e.g., logic circuits (such as microprocessors), located outside of the memory array. One problem associated with manufacturing such complex devices is that some designers and manufacturing engineers tend to treat the regions outside the memory array and the memory array itself as completely separate items, each with their own unique design rules and process flows. As a result, in some cases, manufacturing such complex devices is not as cost-effective or efficient as it could be. For example, by independently focusing on one region to the exclusion of the other, additional manufacturing operations may be performed only in that one region, which tends to require additional manufacturing time, makes the resulting device more costly, and may lead to decreased product yields.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.